The prior art thin-film insulated-gate field-effect transistor used in an active-matrix liquid-crystal electro-optical device is constructed as shown in FIG. 2. A blocking layer 8 is formed on an insulating substrate 9. A semiconductor layer having a source 4, a drain 5, and a channel region 3 is formed on the blocking layer 8. A gate-insulating film 2 and a gate electrode i are laminated on the semiconductor layer. An interlayer insulating film 12 is formed on the gate-insulating film 2 and on the gate electrode 1. A source electrode 6 and a drain electrode 7 are formed on the interlayer insulating film 12 and on the semiconductor layer.
This prior art insulated-gate FET is manufactured in the sequence described now. First, the blocking layer 8 is formed on the glass substrate 9 by sputtering while using SiO.sub.z as a target. Then, the semiconductor layer is formed by plasma-assisted CVD and patterned to form the semiconductor layer which will have the source, drain, and channel region. Then, silicon oxide is sputtered to form the gate-insulating film 2. Subsequently, an electrically conductive layer which is heavily doped with phosphorus and used to form the gate electrode is formed by low-pressure CVD. The conductive layer is then patterned to form the gate electrode 1. Thereafter, dopant ions are implanted while using the gate electrode as a mask, so that the source 4 and the drain 5 are fabricated. Then, the laminate is thermally treated to activate it.
In the insulated-gate FET fabricated in this way, the length of the gate electrode 1 taken-in the longitudinal direction of the channel is substantially identical with the channel length, indicated by 10. In the case of the n-channel structure, the current-voltage characteristic of the FET of this structure is shown in FIG. 3. This FET has the disadvantage that in the reverse bias region 13, the leakage current increases with increasing the voltage applied between the source and drain. Where this device is used in an active-matrix liquid-crystal electro-optical device, if the leakage current increases in this way, the electric charge stored in a liquid crystal 29 by a writing current 30 is discharged as a leakage current 31 through the leaking portion of the device during the non-writing period, as shown in FIG. 5(A). In this manner, it has been impossible to obtain Mood contrast.
A conventional method of solving this problem is to add a capacitor 32 for holding electric charge, as shown in FIG. 5(B). However, in order to form such capacitors, capacitive electrodes made of metal interconnects are needed. This results in a decrease in the aperture ratio. Also, it is reported that the aperture ratio is improved by fabricating the capacitors from transparent electrodes of ITO. Nonetheless, this scheme necessitates an excess process and hence has not enjoyed popularity.
Where only one of the source and drain of this insulated-gate FET is connected with a capacitive device or a capacitor and this transistor is used as a switching device, e.g., in the case of a well-known dynamic random access memory (DRAM) of the 1 transistor/cell type or in the case of an active liquid crystal display having pixels each of which has the circuit shown in FIG. 5(A) or 5(B), it is known that the voltage at the capacitor device is varied by the existence of a parasitic capacitance between the gate electrode and the drain or source.
The variation V in this voltage is in proportion to the gate voltage V.sub.G and to the parasitic capacitance and is in inverse proportion to the sum of the capacitance of the capacitive device and the parasitic capacitance. Therefore, it is customary to fabricate the transistor by the self-aligning technology to reduce the parasitic capacitance, thus suppressing variations in the voltage. However, as the dimensions of devices decrease, the contribution of the parasitic capacitance becomes so large that it can no longer be neglected even if the self-aligning process is exploited.
In an attempt to reduce the variation V, a new method has been proposed. In particular, as shown in FIG. 5(B), a capacitor other than the proper capacitive device is connected in parallel to increase the apparent capacitance of the capacitive device. As described previously, however, the increase in the area of the capacitor cannot be neglected for DRAMs. The decrease in the numerical aperture cannot be neglected for liquid-crystal displays.